For example, Japanese Patent Application Laid-Open Publication No. 2004-180188 (Patent Document 1) discloses a clock and data recovery circuit enabling improvement of jitter tolerance and the like. In the clock and data recovery circuit, an edge of data and an edge of a clock are compared with each other, and in a case where a distance therebetween is shorter than a reference value, recovery of a clock is performed by conducting control such that the edge of the clock is kept away from the edge of data.
And, “12 Gb/s Duobinary Signaling with x2 Oversampled Edge Equalization”, 2005 IEEE International Solid-State Circuits Conference Digest of Technical Papers, Feb. 7, 2005, pp. 70-71 (Non-Patent Document 1) discloses a configuration of a transmission system utilizing a Duobinary transmission method. In the transmission system, binary data (1, 0) from a transmitter side is transmitted to a receiving circuit using the Duobinary transmission method and recovery of a clock signal and a data signal is performed in the receiving circuit. Recovery of the clock signal is performed by detecting a point of crossing in an intermediate level of amplitude of an input signal by the clock recovery circuit. Recovery of the data signal is performed by comparison and determination between the amplitude of the input signal and two reference voltages (intermediate amplitude levels ±Vref) at a timing of a recovered clock signal. And thereby, ternary data (2, 1, 0) can be obtained by the comparison and determination and original binary data (1, 0) is recovered by decoding the ternary data.